OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [rtl/] - Rev 25

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
25 Converted timer B to be a non-reloadable watchdog timer. dgisselq 2900d 15h /s6soc/trunk/rtl/
24 Made the ziptimer autoreload feature a parameter (dis)abled option. dgisselq 2900d 15h /s6soc/trunk/rtl/
23 Fixed a bug which caused every instruction to be loaded/prefetched twice. dgisselq 2900d 15h /s6soc/trunk/rtl/
16 Bug fix. This release fixes several bugs associated with transitioning from
user mode to supervisor mode while running from flash memory. This also
rewires TIMER-B into a watch-dog timer, and adjusts the LED's to be an
indicator of interrupts and whether or not the CPU has stalled or not as well.		 dgisselq 2904d 14h /s6soc/trunk/rtl/
13 Fixed a nasty parameter problem between toplevel and txuart. The UART
transmitter now both works (again), and properly generates the required
interrupts. This also finishes the fixes to the alternate toplevel file,
alttop.v, that should've been fixed in the last release.		 dgisselq 2910d 08h /s6soc/trunk/rtl/
12 The UART and PWM audio now work. This includes the changes to make that
happen, as well as the source code for some UART and PWM demo programs.		 dgisselq 2911d 05h /s6soc/trunk/rtl/
11 Runs on hardware now! Added proper pinouts, pipelined wishbone command
interface sufficient for loading the flash, a loader to load the flash,
and verified that they work.		 dgisselq 2912d 03h /s6soc/trunk/rtl/
8 First pseudo-running version. The alternate configuration (not the main one)
has been initially tested. wbregs works for reading/writing registers,
so it is now possible to test the peripherals.		 dgisselq 2917d 04h /s6soc/trunk/rtl/
7 Created/added an initial specification. Updated/corrected several copywrite
notices.		 dgisselq 2917d 19h /s6soc/trunk/rtl/
5 These two are my first attempt(s) at a secondary project file, one that can
run as an alternate to the main file but that gives more access to the hardware,
such as programming access to the flash.		 dgisselq 2938d 14h /s6soc/trunk/rtl/
4 Lots of updates, as part of actually making this work on hardware. Not there
yet, so this is still pre-alpha.		 dgisselq 2938d 14h /s6soc/trunk/rtl/
3 Updated date. dgisselq 2938d 14h /s6soc/trunk/rtl/
2 The initial check in--all the files that will make this SoC work. dgisselq 2949d 09h /s6soc/trunk/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.