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[/] [s6soc/] [trunk/] [rtl/] - Rev 36

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Rev Log message Author Age Path
35 Minor updates and tweaks, primarily fixing the none_sel signal when the
RTC, scope, or ICAPE interface are not present.		 dgisselq 3049d 18h /s6soc/trunk/rtl/
33 Adjusted the defaults, so that more values have defined default values. dgisselq 3049d 19h /s6soc/trunk/rtl/
32 Removed an undefined value from o_lcd[2] setting. dgisselq 3049d 19h /s6soc/trunk/rtl/
31 Fixed a bug caught by Verilator. dgisselq 3049d 19h /s6soc/trunk/rtl/
30 Brings the CPU up to date with the rest of the ZipCPU distribution. dgisselq 3049d 19h /s6soc/trunk/rtl/
28 Fixed a small lint bug associated with the scope vs the compressed scope. dgisselq 3054d 05h /s6soc/trunk/rtl/
25 Converted timer B to be a non-reloadable watchdog timer. dgisselq 3054d 06h /s6soc/trunk/rtl/
24 Made the ziptimer autoreload feature a parameter (dis)abled option. dgisselq 3054d 06h /s6soc/trunk/rtl/
23 Fixed a bug which caused every instruction to be loaded/prefetched twice. dgisselq 3054d 06h /s6soc/trunk/rtl/
16 Bug fix. This release fixes several bugs associated with transitioning from
user mode to supervisor mode while running from flash memory. This also
rewires TIMER-B into a watch-dog timer, and adjusts the LED's to be an
indicator of interrupts and whether or not the CPU has stalled or not as well.		 dgisselq 3058d 05h /s6soc/trunk/rtl/
13 Fixed a nasty parameter problem between toplevel and txuart. The UART
transmitter now both works (again), and properly generates the required
interrupts. This also finishes the fixes to the alternate toplevel file,
alttop.v, that should've been fixed in the last release.		 dgisselq 3063d 23h /s6soc/trunk/rtl/
12 The UART and PWM audio now work. This includes the changes to make that
happen, as well as the source code for some UART and PWM demo programs.		 dgisselq 3064d 20h /s6soc/trunk/rtl/
11 Runs on hardware now! Added proper pinouts, pipelined wishbone command
interface sufficient for loading the flash, a loader to load the flash,
and verified that they work.		 dgisselq 3065d 18h /s6soc/trunk/rtl/
8 First pseudo-running version. The alternate configuration (not the main one)
has been initially tested. wbregs works for reading/writing registers,
so it is now possible to test the peripherals.		 dgisselq 3070d 19h /s6soc/trunk/rtl/
7 Created/added an initial specification. Updated/corrected several copywrite
notices.		 dgisselq 3071d 10h /s6soc/trunk/rtl/
5 These two are my first attempt(s) at a secondary project file, one that can
run as an alternate to the main file but that gives more access to the hardware,
such as programming access to the flash.		 dgisselq 3092d 05h /s6soc/trunk/rtl/
4 Lots of updates, as part of actually making this work on hardware. Not there
yet, so this is still pre-alpha.		 dgisselq 3092d 05h /s6soc/trunk/rtl/
3 Updated date. dgisselq 3092d 05h /s6soc/trunk/rtl/
2 The initial check in--all the files that will make this SoC work. dgisselq 3103d 00h /s6soc/trunk/rtl/

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