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[/] [s6soc/] [trunk/] [rtl/] [altbusmaster.v] - Rev 51

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51 Latest RTL changes, adding 20 cycles/instruction to CPU dgisselq 2131d 18h /s6soc/trunk/rtl/altbusmaster.v
46 Added missing files from the 8b branch, deleted unneeded files dgisselq 2150d 18h /s6soc/trunk/rtl/altbusmaster.v
32 Removed an undefined value from o_lcd[2] setting. dgisselq 2449d 07h /s6soc/trunk/rtl/altbusmaster.v
25 Converted timer B to be a non-reloadable watchdog timer. dgisselq 2453d 18h /s6soc/trunk/rtl/altbusmaster.v
13 Fixed a nasty parameter problem between toplevel and txuart. The UART
transmitter now both works (again), and properly generates the required
interrupts. This also finishes the fixes to the alternate toplevel file,
alttop.v, that should've been fixed in the last release.
dgisselq 2463d 11h /s6soc/trunk/rtl/altbusmaster.v
11 Runs on hardware now! Added proper pinouts, pipelined wishbone command
interface sufficient for loading the flash, a loader to load the flash,
and verified that they work.
dgisselq 2465d 07h /s6soc/trunk/rtl/altbusmaster.v
8 First pseudo-running version. The alternate configuration (not the main one)
has been initially tested. wbregs works for reading/writing registers,
so it is now possible to test the peripherals.
dgisselq 2470d 08h /s6soc/trunk/rtl/altbusmaster.v
5 These two are my first attempt(s) at a secondary project file, one that can
run as an alternate to the main file but that gives more access to the hardware,
such as programming access to the flash.
dgisselq 2491d 17h /s6soc/trunk/rtl/altbusmaster.v

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