OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [rtl/] [builddate.v] - Rev 16

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
16 Bug fix. This release fixes several bugs associated with transitioning from
user mode to supervisor mode while running from flash memory. This also
rewires TIMER-B into a watch-dog timer, and adjusts the LED's to be an
indicator of interrupts and whether or not the CPU has stalled or not as well.
dgisselq 2972d 03h /s6soc/trunk/rtl/builddate.v
13 Fixed a nasty parameter problem between toplevel and txuart. The UART
transmitter now both works (again), and properly generates the required
interrupts. This also finishes the fixes to the alternate toplevel file,
alttop.v, that should've been fixed in the last release.
dgisselq 2977d 21h /s6soc/trunk/rtl/builddate.v
11 Runs on hardware now! Added proper pinouts, pipelined wishbone command
interface sufficient for loading the flash, a loader to load the flash,
and verified that they work.
dgisselq 2979d 16h /s6soc/trunk/rtl/builddate.v
8 First pseudo-running version. The alternate configuration (not the main one)
has been initially tested. wbregs works for reading/writing registers,
so it is now possible to test the peripherals.
dgisselq 2984d 17h /s6soc/trunk/rtl/builddate.v
7 Created/added an initial specification. Updated/corrected several copywrite
notices.
dgisselq 2985d 08h /s6soc/trunk/rtl/builddate.v
3 Updated date. dgisselq 3006d 03h /s6soc/trunk/rtl/builddate.v
2 The initial check in--all the files that will make this SoC work. dgisselq 3016d 22h /s6soc/trunk/rtl/builddate.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.