URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [rtl/] [cpu/] [idecode.v] - Rev 51

Rev	Log message	Author	Age	Path
51	Latest RTL changes, adding 20 cycles/instruction to CPU	dgisselq	2585d 14h	/s6soc/trunk/rtl/cpu/idecode.v
46	Added missing files from the 8b branch, deleted unneeded files	dgisselq	2604d 14h	/s6soc/trunk/rtl/cpu/idecode.v
30	Brings the CPU up to date with the rest of the ZipCPU distribution.	dgisselq	2903d 03h	/s6soc/trunk/rtl/cpu/idecode.v
11	Runs on hardware now! Added proper pinouts, pipelined wishbone command interface sufficient for loading the flash, a loader to load the flash, and verified that they work.	dgisselq	2919d 03h	/s6soc/trunk/rtl/cpu/idecode.v
2	The initial check in--all the files that will make this SoC work.	dgisselq	2956d 08h	/s6soc/trunk/rtl/cpu/idecode.v