OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [rtl/] [cpu/] [zipcpu.v] - Rev 20

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
16 Bug fix. This release fixes several bugs associated with transitioning from
user mode to supervisor mode while running from flash memory. This also
rewires TIMER-B into a watch-dog timer, and adjusts the LED's to be an
indicator of interrupts and whether or not the CPU has stalled or not as well.
dgisselq 2918d 01h /s6soc/trunk/rtl/cpu/zipcpu.v
11 Runs on hardware now! Added proper pinouts, pipelined wishbone command
interface sufficient for loading the flash, a loader to load the flash,
and verified that they work.
dgisselq 2925d 14h /s6soc/trunk/rtl/cpu/zipcpu.v
7 Created/added an initial specification. Updated/corrected several copywrite
notices.
dgisselq 2931d 05h /s6soc/trunk/rtl/cpu/zipcpu.v
2 The initial check in--all the files that will make this SoC work. dgisselq 2962d 19h /s6soc/trunk/rtl/cpu/zipcpu.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.