URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [sw/] [host/] - Rev 17

Rev	Log message	Author	Age	Path
14	Modified the loader so that it will load even if there are RAM variables in the load, just as long as they aren't anything but zero. (The startup code, however, doesn't clear memory to match--so be sure to initialize all variables.)	dgisselq	2927d 14h	/s6soc/trunk/sw/host/
12	The UART and PWM audio now work. This includes the changes to make that happen, as well as the source code for some UART and PWM demo programs.	dgisselq	2928d 11h	/s6soc/trunk/sw/host/
11	Runs on hardware now! Added proper pinouts, pipelined wishbone command interface sufficient for loading the flash, a loader to load the flash, and verified that they work.	dgisselq	2929d 09h	/s6soc/trunk/sw/host/
8	First pseudo-running version. The alternate configuration (not the main one) has been initially tested. wbregs works for reading/writing registers, so it is now possible to test the peripherals.	dgisselq	2934d 10h	/s6soc/trunk/sw/host/