URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [sw/] [host] - Rev 26

Rev	Log message	Author	Age	Path
26	Modified to be able to handle different load from virtual addresses. This enables the bootloader capability.	dgisselq	2909d 13h	/s6soc/trunk/sw/host
19	Addition of dumpuart.cpp to dump the UART transactions to a FILE (method of debugging the board). FLASHDRVR and ZIPLOAD were also updated to handle loading ELF files where the code is longer than a single block.	dgisselq	2913d 12h	/s6soc/trunk/sw/host
14	Modified the loader so that it will load even if there are RAM variables in the load, just as long as they aren't anything but zero. (The startup code, however, doesn't clear memory to match--so be sure to initialize all variables.)	dgisselq	2919d 05h	/s6soc/trunk/sw/host
12	The UART and PWM audio now work. This includes the changes to make that happen, as well as the source code for some UART and PWM demo programs.	dgisselq	2920d 03h	/s6soc/trunk/sw/host
11	Runs on hardware now! Added proper pinouts, pipelined wishbone command interface sufficient for loading the flash, a loader to load the flash, and verified that they work.	dgisselq	2921d 01h	/s6soc/trunk/sw/host
8	First pseudo-running version. The alternate configuration (not the main one) has been initially tested. wbregs works for reading/writing registers, so it is now possible to test the peripherals.	dgisselq	2926d 02h	/s6soc/trunk/sw/host