OpenCores
URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] - Rev 188

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
188 Declared all targets phony to force building. rkastl 4874d 20h /sdhc-sc-core/
187 Unit makefiles modified to reflect new location of Makefile.rules. rkastl 4874d 20h /sdhc-sc-core/
186 Makefile adapted to new paths. rkastl 4874d 20h /sdhc-sc-core/
185 Restructuring as source repository: Moved sources out of src subdirectory. rkastl 4874d 20h /sdhc-sc-core/
184 Removed WbSlave shell (refs #69)
Moved verification sources to grpSdVerification (fixes #70)		 rkastl 4877d 14h /sdhc-sc-core/
183 Removed unneeded wrapper (refs #69)
Sector count increased in TestWbMaster (refs #78)		 rkastl 4877d 14h /sdhc-sc-core/
182 Fixes #60.

Synchronization logic moved to its own unit.		 rkastl 4877d 14h /sdhc-sc-core/
181 Refs #60.

Fix synthesis with seperate WbClkDomain.		 rkastl 4877d 14h /sdhc-sc-core/
180 Moved WbClkDomain to its own unit.
Refs #60.		 rkastl 4877d 14h /sdhc-sc-core/
179 Fixing build:
Added library generation to Makefile.		 rkastl 4877d 14h /sdhc-sc-core/
178 Fixed regression:
Testbenches did not support synchronous reset.		 rkastl 4877d 14h /sdhc-sc-core/
177 Split SdTop into SdClkDomain and SdTop. Refs #60. rkastl 4877d 14h /sdhc-sc-core/
176 Thesis:
Conclusion

Fixes #53,#61.		 rkastl 4877d 14h /sdhc-sc-core/
175 Thesis:

Fixes #45.		 rkastl 4877d 14h /sdhc-sc-core/
174 Thesis:
System integration

Fixes #51.		 rkastl 4877d 14h /sdhc-sc-core/
173 Thesis:
Started with SdController description.

Refs #38.		 rkastl 4877d 14h /sdhc-sc-core/
172 Thesis:
wbclockdomain: refactored and finished.

Fixes #39.		 rkastl 4877d 14h /sdhc-sc-core/
171 Worked on wishbone part of thesis.

Refs #37.
Refs #39.		 rkastl 4877d 14h /sdhc-sc-core/
170 License rewritten to BSD rkastl 4877d 14h /sdhc-sc-core/
169 +sdc file for timing analysis rkastl 4877d 14h /sdhc-sc-core/
168 TbdSd synthesis script reaches timing constraints. rkastl 4877d 14h /sdhc-sc-core/
167 Read+Modify+Write works on HW

+ Fixed CRC status token (not mentioned in simplified spec)
+ Improved TestWbMaster to RMW		 rkastl 4877d 14h /sdhc-sc-core/
166 tbTbdSd: fixed rkastl 4877d 14h /sdhc-sc-core/
165 Only use synchronous high active reset in SDHC-SC-Core. rkastl 4877d 14h /sdhc-sc-core/
164 Headers updated (LGPL, consistent format) rkastl 4877d 14h /sdhc-sc-core/
163 Header-Skript supports writing to file and infile replacement. rkastl 4877d 14h /sdhc-sc-core/
162 Script for generating headers created. rkastl 4877d 14h /sdhc-sc-core/
161 Verification:
CardModel: Check CRC on received data		 rkastl 4877d 14h /sdhc-sc-core/
160 Verification:
Full random read and write single blocks sequence works with
checks.
Checking the CRC in the card model is missing.
Writing at addresses above the card size is missing.
Erasing is missing.		 rkastl 4877d 14h /sdhc-sc-core/
159 Verification:
Further work: Checking RAM Actions and reading data is still
missing		 rkastl 4877d 14h /sdhc-sc-core/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.