URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] - Rev 188

Rev	Log message	Author	Age	Path
168	TbdSd synthesis script reaches timing constraints.	rkastl	4876d 20h	/sdhc-sc-core/
167	Read+Modify+Write works on HW + Fixed CRC status token (not mentioned in simplified spec) + Improved TestWbMaster to RMW	rkastl	4876d 20h	/sdhc-sc-core/
166	tbTbdSd: fixed	rkastl	4876d 20h	/sdhc-sc-core/
165	Only use synchronous high active reset in SDHC-SC-Core.	rkastl	4876d 20h	/sdhc-sc-core/
164	Headers updated (LGPL, consistent format)	rkastl	4876d 20h	/sdhc-sc-core/
163	Header-Skript supports writing to file and infile replacement.	rkastl	4876d 20h	/sdhc-sc-core/
162	Script for generating headers created.	rkastl	4876d 20h	/sdhc-sc-core/
161	Verification: CardModel: Check CRC on received data	rkastl	4876d 20h	/sdhc-sc-core/
160	Verification: Full random read and write single blocks sequence works with checks. Checking the CRC in the card model is missing. Writing at addresses above the card size is missing. Erasing is missing.	rkastl	4876d 20h	/sdhc-sc-core/
159	Verification: Further work: Checking RAM Actions and reading data is still missing	rkastl	4876d 20h	/sdhc-sc-core/