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Rev Log message Author Age Path
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4560d 21h /
26 invalid log files are removed dinesha 4560d 21h /
25 tb.sv is renamed as tb_top dinesha 4560d 21h /
24 Clean Up dinesha 4560d 21h /
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4562d 02h /
22 Pad sdram clock added dinesha 4562d 02h /
21 Clean up dinesha 4562d 03h /
20 8 Bit SDARM support is added dinesha 4563d 21h /
19 8 Bit SDRAM Support added dinesha 4563d 21h /
18 8 Bit SDRAM Support is added dinesha 4563d 21h /
17 micron 8 bit memory models are added into svn dinesha 4563d 21h /
16 8 Bit SDRAM Support is added dinesha 4563d 21h /
15 Port cleanup dinesha 4566d 22h /
14 Unnecessary device config are removed dinesha 4566d 22h /
13 column bit are made progrmmable dinesha 4566d 22h /
12 Column Bits are made programmable dinesha 4566d 23h /
11 SDRAM Specification document added into SVN dinesha 4569d 23h /
10 Waveform files are added into SVN dinesha 4569d 23h /
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4570d 23h /
8 test bench files are added into SVN dinesha 4570d 23h /

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