URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] - Rev 29

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Rev	Log message	Author	Age	Path
29	SDRAM top and core related run file list are added into svn	dinesha	4480d 15h	/
28	SDRAM top and SDRAM Core Golden files are added into SVN	dinesha	4480d 15h	/
27	Golden log file corresponds the SDRAM core level test case are added into svn	dinesha	4481d 13h	/
26	invalid log files are removed	dinesha	4481d 14h	/
25	tb.sv is renamed as tb_top	dinesha	4481d 14h	/
24	Clean Up	dinesha	4481d 14h	/
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	4482d 19h	/
22	Pad sdram clock added	dinesha	4482d 19h	/
21	Clean up	dinesha	4482d 19h	/
20	8 Bit SDARM support is added	dinesha	4484d 14h	/
19	8 Bit SDRAM Support added	dinesha	4484d 14h	/
18	8 Bit SDRAM Support is added	dinesha	4484d 14h	/
17	micron 8 bit memory models are added into svn	dinesha	4484d 14h	/
16	8 Bit SDRAM Support is added	dinesha	4484d 14h	/
15	Port cleanup	dinesha	4487d 15h	/
14	Unnecessary device config are removed	dinesha	4487d 15h	/
13	column bit are made progrmmable	dinesha	4487d 15h	/
12	Column Bits are made programmable	dinesha	4487d 15h	/
11	SDRAM Specification document added into SVN	dinesha	4490d 16h	/
10	Waveform files are added into SVN	dinesha	4490d 16h	/
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4491d 16h	/
8	test bench files are added into SVN	dinesha	4491d 16h	/
7	SDRAM Memory Models are added into SVN	dinesha	4491d 16h	/
6	Golden Log files are added into SVN	dinesha	4491d 16h	/
5	Run files are updated into SVN	dinesha	4491d 16h	/
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4492d 13h	/
3	SDRAM controller core files are checked in	dinesha	4498d 23h	/
2		dinesha	4501d 15h	/
1	The project and the structure was created	root	4505d 15h	/

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Subversion Repositories sdr_ctrl

[/] - Rev 29

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