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Rev Log message Author Age Path
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4491d 10h /
8 test bench files are added into SVN dinesha 4491d 10h /
7 SDRAM Memory Models are added into SVN dinesha 4491d 10h /
6 Golden Log files are added into SVN dinesha 4491d 10h /
5 Run files are updated into SVN dinesha 4491d 10h /
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4492d 07h /
3 SDRAM controller core files are checked in dinesha 4498d 17h /
2 dinesha 4501d 09h /
1 The project and the structure was created root 4505d 09h /

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