URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] - Rev 32

Rev	Log message	Author	Age	Path
32	Debug is enable through +define	dinesha	4486d 12h	/
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4486d 12h	/
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4486d 12h	/
29	SDRAM top and core related run file list are added into svn	dinesha	4486d 12h	/
28	SDRAM top and SDRAM Core Golden files are added into SVN	dinesha	4486d 12h	/
27	Golden log file corresponds the SDRAM core level test case are added into svn	dinesha	4487d 10h	/
26	invalid log files are removed	dinesha	4487d 10h	/
25	tb.sv is renamed as tb_top	dinesha	4487d 11h	/
24	Clean Up	dinesha	4487d 11h	/
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	4488d 16h	/
22	Pad sdram clock added	dinesha	4488d 16h	/
21	Clean up	dinesha	4488d 16h	/
20	8 Bit SDARM support is added	dinesha	4490d 11h	/
19	8 Bit SDRAM Support added	dinesha	4490d 11h	/
18	8 Bit SDRAM Support is added	dinesha	4490d 11h	/
17	micron 8 bit memory models are added into svn	dinesha	4490d 11h	/
16	8 Bit SDRAM Support is added	dinesha	4490d 11h	/
15	Port cleanup	dinesha	4493d 12h	/
14	Unnecessary device config are removed	dinesha	4493d 12h	/
13	column bit are made progrmmable	dinesha	4493d 12h	/