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Rev Log message Author Age Path
34 Removed the older version dinesha 4488d 00h /
33 clean up dinesha 4488d 01h /
32 Debug is enable through +define dinesha 4490d 00h /
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4490d 00h /
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4490d 00h /
29 SDRAM top and core related run file list are added into svn dinesha 4490d 00h /
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4490d 00h /
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4490d 22h /
26 invalid log files are removed dinesha 4490d 22h /
25 tb.sv is renamed as tb_top dinesha 4490d 23h /
24 Clean Up dinesha 4490d 23h /
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4492d 04h /
22 Pad sdram clock added dinesha 4492d 04h /
21 Clean up dinesha 4492d 04h /
20 8 Bit SDARM support is added dinesha 4493d 23h /
19 8 Bit SDRAM Support added dinesha 4493d 23h /
18 8 Bit SDRAM Support is added dinesha 4493d 23h /
17 micron 8 bit memory models are added into svn dinesha 4493d 23h /
16 8 Bit SDRAM Support is added dinesha 4493d 23h /
15 Port cleanup dinesha 4496d 23h /
14 Unnecessary device config are removed dinesha 4497d 00h /
13 column bit are made progrmmable dinesha 4497d 00h /
12 Column Bits are made programmable dinesha 4497d 00h /
11 SDRAM Specification document added into SVN dinesha 4500d 01h /
10 Waveform files are added into SVN dinesha 4500d 01h /
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4501d 00h /
8 test bench files are added into SVN dinesha 4501d 01h /
7 SDRAM Memory Models are added into SVN dinesha 4501d 01h /
6 Golden Log files are added into SVN dinesha 4501d 01h /
5 Run files are updated into SVN dinesha 4501d 01h /

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