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Rev Log message Author Age Path
36 Clean up dinesha 4553d 00h /
35 Updated the New Documents - ver 0.1 dinesha 4553d 02h /
34 Removed the older version dinesha 4553d 02h /
33 clean up dinesha 4553d 02h /
32 Debug is enable through +define dinesha 4555d 01h /
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4555d 01h /
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4555d 02h /
29 SDRAM top and core related run file list are added into svn dinesha 4555d 02h /
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4555d 02h /
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4556d 00h /
26 invalid log files are removed dinesha 4556d 00h /
25 tb.sv is renamed as tb_top dinesha 4556d 00h /
24 Clean Up dinesha 4556d 00h /
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4557d 05h /
22 Pad sdram clock added dinesha 4557d 05h /
21 Clean up dinesha 4557d 05h /
20 8 Bit SDARM support is added dinesha 4559d 00h /
19 8 Bit SDRAM Support added dinesha 4559d 00h /
18 8 Bit SDRAM Support is added dinesha 4559d 00h /
17 micron 8 bit memory models are added into svn dinesha 4559d 00h /

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