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Rev Log message Author Age Path
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4414d 00h /
36 Clean up dinesha 4414d 15h /
35 Updated the New Documents - ver 0.1 dinesha 4414d 17h /
34 Removed the older version dinesha 4414d 17h /
33 clean up dinesha 4414d 17h /
32 Debug is enable through +define dinesha 4416d 16h /
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4416d 16h /
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4416d 16h /
29 SDRAM top and core related run file list are added into svn dinesha 4416d 16h /
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4416d 17h /
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4417d 15h /
26 invalid log files are removed dinesha 4417d 15h /
25 tb.sv is renamed as tb_top dinesha 4417d 15h /
24 Clean Up dinesha 4417d 15h /
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4418d 20h /
22 Pad sdram clock added dinesha 4418d 20h /
21 Clean up dinesha 4418d 20h /
20 8 Bit SDARM support is added dinesha 4420d 15h /
19 8 Bit SDRAM Support added dinesha 4420d 15h /
18 8 Bit SDRAM Support is added dinesha 4420d 15h /

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