Subversion Repositories sdr_ctrl

[/] - Rev 39


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
39 Test Bench upgradation with bigger data burst size dinesha 4146d 20h /
38 Port Name clean up dinesha 4148d 01h /
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4148d 03h /
36 Clean up dinesha 4148d 18h /
35 Updated the New Documents - ver 0.1 dinesha 4148d 19h /
34 Removed the older version dinesha 4148d 19h /
33 clean up dinesha 4148d 20h /
32 Debug is enable through +define dinesha 4150d 19h /
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4150d 19h /
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4150d 19h /
29 SDRAM top and core related run file list are added into svn dinesha 4150d 19h /
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4150d 19h /
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4151d 17h /
26 invalid log files are removed dinesha 4151d 17h /
25 is renamed as tb_top dinesha 4151d 18h /
24 Clean Up dinesha 4151d 18h /
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4152d 23h /
22 Pad sdram clock added dinesha 4152d 23h /
21 Clean up dinesha 4152d 23h /
20 8 Bit SDARM support is added dinesha 4154d 18h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2023, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.