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Rev Log message Author Age Path
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4018d 03h /
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4018d 05h /
42 Bug fix in read access is fixed dinesha 4018d 05h /
41 Updated Spec ver 0.1 is added back to svn dinesha 4018d 07h /
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4019d 00h /
39 Test Bench upgradation with bigger data burst size dinesha 4019d 00h /
38 Port Name clean up dinesha 4020d 05h /
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4020d 07h /
36 Clean up dinesha 4020d 21h /
35 Updated the New Documents - ver 0.1 dinesha 4020d 23h /
34 Removed the older version dinesha 4020d 23h /
33 clean up dinesha 4020d 23h /
32 Debug is enable through +define dinesha 4022d 22h /
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4022d 22h /
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4022d 23h /
29 SDRAM top and core related run file list are added into svn dinesha 4022d 23h /
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4022d 23h /
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4023d 21h /
26 invalid log files are removed dinesha 4023d 21h /
25 tb.sv is renamed as tb_top dinesha 4023d 21h /

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