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Rev Log message Author Age Path
50 Bug fix the request length is fixe dinesha 4509d 19h /
49 clean up dinesha 4510d 18h /
48 top-level cleanup dinesha 4510d 18h /
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4510d 18h /
46 test bench upgrade + rtl cleanup dinesha 4512d 18h /
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4512d 23h /
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4514d 21h /
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4514d 23h /
42 Bug fix in read access is fixed dinesha 4514d 23h /
41 Updated Spec ver 0.1 is added back to svn dinesha 4515d 00h /
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4515d 17h /
39 Test Bench upgradation with bigger data burst size dinesha 4515d 17h /
38 Port Name clean up dinesha 4516d 22h /
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4517d 00h /
36 Clean up dinesha 4517d 15h /
35 Updated the New Documents - ver 0.1 dinesha 4517d 17h /
34 Removed the older version dinesha 4517d 17h /
33 clean up dinesha 4517d 17h /
32 Debug is enable through +define dinesha 4519d 16h /
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4519d 16h /

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