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Subversion Repositories sdr_ctrl

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Rev Log message Author Age Path
51 FPGA relating timing optimisation done dinesha 4476d 02h /
50 Bug fix the request length is fixe dinesha 4478d 05h /
49 clean up dinesha 4479d 04h /
48 top-level cleanup dinesha 4479d 04h /
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4479d 04h /
46 test bench upgrade + rtl cleanup dinesha 4481d 05h /
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4481d 09h /
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4483d 08h /
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4483d 09h /
42 Bug fix in read access is fixed dinesha 4483d 09h /
41 Updated Spec ver 0.1 is added back to svn dinesha 4483d 11h /
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4484d 04h /
39 Test Bench upgradation with bigger data burst size dinesha 4484d 04h /
38 Port Name clean up dinesha 4485d 09h /
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4485d 11h /
36 Clean up dinesha 4486d 02h /
35 Updated the New Documents - ver 0.1 dinesha 4486d 03h /
34 Removed the older version dinesha 4486d 03h /
33 clean up dinesha 4486d 04h /
32 Debug is enable through +define dinesha 4488d 03h /
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4488d 03h /
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4488d 03h /
29 SDRAM top and core related run file list are added into svn dinesha 4488d 03h /
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4488d 03h /
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4489d 01h /
26 invalid log files are removed dinesha 4489d 01h /
25 tb.sv is renamed as tb_top dinesha 4489d 02h /
24 Clean Up dinesha 4489d 02h /
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4490d 07h /
22 Pad sdram clock added dinesha 4490d 07h /

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