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Rev Log message Author Age Path
53 Test bench upgradation dinesha 4548d 01h /
52 Documentation update for request control and transfer control block dinesha 4548d 01h /
51 FPGA relating timing optimisation done dinesha 4548d 01h /
50 Bug fix the request length is fixe dinesha 4550d 05h /
49 clean up dinesha 4551d 04h /
48 top-level cleanup dinesha 4551d 04h /
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4551d 04h /
46 test bench upgrade + rtl cleanup dinesha 4553d 05h /
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4553d 09h /
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4555d 07h /
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4555d 09h /
42 Bug fix in read access is fixed dinesha 4555d 09h /
41 Updated Spec ver 0.1 is added back to svn dinesha 4555d 11h /
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4556d 04h /
39 Test Bench upgradation with bigger data burst size dinesha 4556d 04h /
38 Port Name clean up dinesha 4557d 09h /
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4557d 10h /
36 Clean up dinesha 4558d 01h /
35 Updated the New Documents - ver 0.1 dinesha 4558d 03h /
34 Removed the older version dinesha 4558d 03h /

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