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Rev Log message Author Age Path
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4361d 16h /
65 Updated Log file with CAS latency support 4,5 dinesha 4362d 00h /
64 CAS Latency support added for 4,5 dinesha 4362d 00h /
63 FPGA Bench mark results are added dinesha 4480d 23h /
62 Synthesis constraint for simplify dinesha 4480d 23h /
61 RTL file list are added into SVN dinesha 4481d 00h /
60 warning cleanup dinesha 4481d 00h /
59 Control path request and data are register now for better FPGA timing dinesha 4481d 00h /
58 Read Data is register on RD_FAST=0 case dinesha 4481d 00h /
57 Synthesis constraints are added dinesha 4481d 14h /
56 FPGA Synth optimisation dinesha 4481d 15h /
55 FPGA Synthesis timing optimisation dinesha 4481d 16h /
54 FPGA Timing Optimisation dinesha 4484d 13h /
53 Test bench upgradation dinesha 4485d 14h /
52 Documentation update for request control and transfer control block dinesha 4485d 14h /
51 FPGA relating timing optimisation done dinesha 4485d 14h /
50 Bug fix the request length is fixe dinesha 4487d 18h /
49 clean up dinesha 4488d 17h /
48 top-level cleanup dinesha 4488d 17h /
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4488d 17h /
46 test bench upgrade + rtl cleanup dinesha 4490d 18h /
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4490d 22h /
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4492d 20h /
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4492d 22h /
42 Bug fix in read access is fixed dinesha 4492d 22h /
41 Updated Spec ver 0.1 is added back to svn dinesha 4493d 00h /
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4493d 16h /
39 Test Bench upgradation with bigger data burst size dinesha 4493d 17h /
38 Port Name clean up dinesha 4494d 22h /
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4494d 23h /

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