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Rev Log message Author Age Path
46 test bench upgrade + rtl cleanup dinesha 4491d 05h /
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4491d 09h /
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4493d 07h /
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4493d 09h /
42 Bug fix in read access is fixed dinesha 4493d 09h /
41 Updated Spec ver 0.1 is added back to svn dinesha 4493d 10h /
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4494d 03h /
39 Test Bench upgradation with bigger data burst size dinesha 4494d 03h /
38 Port Name clean up dinesha 4495d 08h /
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4495d 10h /

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