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Rev Log message Author Age Path
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 3565d 21h /
67 time scale removed dinesha 3635d 19h /
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 3883d 20h /
65 Updated Log file with CAS latency support 4,5 dinesha 3884d 04h /
64 CAS Latency support added for 4,5 dinesha 3884d 04h /
63 FPGA Bench mark results are added dinesha 4003d 03h /
62 Synthesis constraint for simplify dinesha 4003d 03h /
61 RTL file list are added into SVN dinesha 4003d 04h /
60 warning cleanup dinesha 4003d 04h /
59 Control path request and data are register now for better FPGA timing dinesha 4003d 04h /
58 Read Data is register on RD_FAST=0 case dinesha 4003d 04h /
57 Synthesis constraints are added dinesha 4003d 19h /
56 FPGA Synth optimisation dinesha 4003d 20h /
55 FPGA Synthesis timing optimisation dinesha 4003d 20h /
54 FPGA Timing Optimisation dinesha 4006d 18h /
53 Test bench upgradation dinesha 4007d 18h /
52 Documentation update for request control and transfer control block dinesha 4007d 18h /
51 FPGA relating timing optimisation done dinesha 4007d 18h /
50 Bug fix the request length is fixe dinesha 4009d 22h /
49 clean up dinesha 4010d 21h /

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