OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] - Rev 71

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
71 Warning cleanup dinesha 4034d 00h /
70 Warning Cleanup dinesha 4034d 00h /
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4034d 01h /
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 4034d 01h /
67 time scale removed dinesha 4103d 23h /
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4352d 00h /
65 Updated Log file with CAS latency support 4,5 dinesha 4352d 08h /
64 CAS Latency support added for 4,5 dinesha 4352d 08h /
63 FPGA Bench mark results are added dinesha 4471d 07h /
62 Synthesis constraint for simplify dinesha 4471d 07h /
61 RTL file list are added into SVN dinesha 4471d 08h /
60 warning cleanup dinesha 4471d 08h /
59 Control path request and data are register now for better FPGA timing dinesha 4471d 08h /
58 Read Data is register on RD_FAST=0 case dinesha 4471d 08h /
57 Synthesis constraints are added dinesha 4471d 22h /
56 FPGA Synth optimisation dinesha 4471d 23h /
55 FPGA Synthesis timing optimisation dinesha 4472d 00h /
54 FPGA Timing Optimisation dinesha 4474d 21h /
53 Test bench upgradation dinesha 4475d 22h /
52 Documentation update for request control and transfer control block dinesha 4475d 22h /
51 FPGA relating timing optimisation done dinesha 4475d 22h /
50 Bug fix the request length is fixe dinesha 4478d 02h /
49 clean up dinesha 4479d 01h /
48 top-level cleanup dinesha 4479d 01h /
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4479d 01h /
46 test bench upgrade + rtl cleanup dinesha 4481d 02h /
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4481d 06h /
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4483d 04h /
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4483d 06h /
42 Bug fix in read access is fixed dinesha 4483d 06h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.