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Subversion Repositories sdr_ctrl

[/] - Rev 73

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Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 1139d 03h /
72 Command Clean up for model-sim mode dinesha 4132d 12h /
71 Warning cleanup dinesha 4184d 04h /
70 Warning Cleanup dinesha 4184d 04h /
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4184d 05h /
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 4184d 05h /
67 time scale removed dinesha 4254d 03h /
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4502d 04h /
65 Updated Log file with CAS latency support 4,5 dinesha 4502d 12h /
64 CAS Latency support added for 4,5 dinesha 4502d 12h /
63 FPGA Bench mark results are added dinesha 4621d 11h /
62 Synthesis constraint for simplify dinesha 4621d 11h /
61 RTL file list are added into SVN dinesha 4621d 12h /
60 warning cleanup dinesha 4621d 12h /
59 Control path request and data are register now for better FPGA timing dinesha 4621d 12h /
58 Read Data is register on RD_FAST=0 case dinesha 4621d 12h /
57 Synthesis constraints are added dinesha 4622d 02h /
56 FPGA Synth optimisation dinesha 4622d 04h /
55 FPGA Synthesis timing optimisation dinesha 4622d 04h /
54 FPGA Timing Optimisation dinesha 4625d 02h /
53 Test bench upgradation dinesha 4626d 02h /
52 Documentation update for request control and transfer control block dinesha 4626d 02h /
51 FPGA relating timing optimisation done dinesha 4626d 02h /
50 Bug fix the request length is fixe dinesha 4628d 06h /
49 clean up dinesha 4629d 05h /
48 top-level cleanup dinesha 4629d 05h /
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4629d 05h /
46 test bench upgrade + rtl cleanup dinesha 4631d 06h /
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4631d 10h /
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4633d 08h /

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