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[/] [sdr_ctrl/] - Rev 16

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Rev Log message Author Age Path
16 8 Bit SDRAM Support is added dinesha 4533d 11h /sdr_ctrl/
15 Port cleanup dinesha 4536d 12h /sdr_ctrl/
14 Unnecessary device config are removed dinesha 4536d 12h /sdr_ctrl/
13 column bit are made progrmmable dinesha 4536d 12h /sdr_ctrl/
12 Column Bits are made programmable dinesha 4536d 12h /sdr_ctrl/
11 SDRAM Specification document added into SVN dinesha 4539d 13h /sdr_ctrl/
10 Waveform files are added into SVN dinesha 4539d 13h /sdr_ctrl/
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4540d 13h /sdr_ctrl/
8 test bench files are added into SVN dinesha 4540d 13h /sdr_ctrl/
7 SDRAM Memory Models are added into SVN dinesha 4540d 13h /sdr_ctrl/
6 Golden Log files are added into SVN dinesha 4540d 13h /sdr_ctrl/
5 Run files are updated into SVN dinesha 4540d 13h /sdr_ctrl/
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4541d 10h /sdr_ctrl/
3 SDRAM controller core files are checked in dinesha 4547d 20h /sdr_ctrl/
2 dinesha 4550d 13h /sdr_ctrl/
1 The project and the structure was created root 4554d 12h /sdr_ctrl/

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