OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 18

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
18 8 Bit SDRAM Support is added dinesha 4021d 19h /sdr_ctrl/
17 micron 8 bit memory models are added into svn dinesha 4021d 19h /sdr_ctrl/
16 8 Bit SDRAM Support is added dinesha 4021d 19h /sdr_ctrl/
15 Port cleanup dinesha 4024d 19h /sdr_ctrl/
14 Unnecessary device config are removed dinesha 4024d 19h /sdr_ctrl/
13 column bit are made progrmmable dinesha 4024d 20h /sdr_ctrl/
12 Column Bits are made programmable dinesha 4024d 20h /sdr_ctrl/
11 SDRAM Specification document added into SVN dinesha 4027d 21h /sdr_ctrl/
10 Waveform files are added into SVN dinesha 4027d 21h /sdr_ctrl/
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4028d 20h /sdr_ctrl/
8 test bench files are added into SVN dinesha 4028d 20h /sdr_ctrl/
7 SDRAM Memory Models are added into SVN dinesha 4028d 20h /sdr_ctrl/
6 Golden Log files are added into SVN dinesha 4028d 21h /sdr_ctrl/
5 Run files are updated into SVN dinesha 4028d 21h /sdr_ctrl/
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4029d 18h /sdr_ctrl/
3 SDRAM controller core files are checked in dinesha 4036d 04h /sdr_ctrl/
2 dinesha 4038d 20h /sdr_ctrl/
1 The project and the structure was created root 4042d 20h /sdr_ctrl/

powered by: WebSVN 2.1.0

© copyright 1999-2023 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.