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[/] [sdr_ctrl/] - Rev 25

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Rev Log message Author Age Path
25 tb.sv is renamed as tb_top dinesha 4501d 17h /sdr_ctrl/
24 Clean Up dinesha 4501d 17h /sdr_ctrl/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4502d 23h /sdr_ctrl/
22 Pad sdram clock added dinesha 4502d 23h /sdr_ctrl/
21 Clean up dinesha 4502d 23h /sdr_ctrl/
20 8 Bit SDARM support is added dinesha 4504d 17h /sdr_ctrl/
19 8 Bit SDRAM Support added dinesha 4504d 17h /sdr_ctrl/
18 8 Bit SDRAM Support is added dinesha 4504d 17h /sdr_ctrl/
17 micron 8 bit memory models are added into svn dinesha 4504d 18h /sdr_ctrl/
16 8 Bit SDRAM Support is added dinesha 4504d 18h /sdr_ctrl/
15 Port cleanup dinesha 4507d 18h /sdr_ctrl/
14 Unnecessary device config are removed dinesha 4507d 18h /sdr_ctrl/
13 column bit are made progrmmable dinesha 4507d 19h /sdr_ctrl/
12 Column Bits are made programmable dinesha 4507d 19h /sdr_ctrl/
11 SDRAM Specification document added into SVN dinesha 4510d 20h /sdr_ctrl/
10 Waveform files are added into SVN dinesha 4510d 20h /sdr_ctrl/
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4511d 19h /sdr_ctrl/
8 test bench files are added into SVN dinesha 4511d 19h /sdr_ctrl/
7 SDRAM Memory Models are added into SVN dinesha 4511d 19h /sdr_ctrl/
6 Golden Log files are added into SVN dinesha 4511d 20h /sdr_ctrl/

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