URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 28

Rev	Log message	Author	Age	Path
28	SDRAM top and SDRAM Core Golden files are added into SVN	dinesha	5314d 06h	/sdr_ctrl/
27	Golden log file corresponds the SDRAM core level test case are added into svn	dinesha	5315d 04h	/sdr_ctrl/
26	invalid log files are removed	dinesha	5315d 04h	/sdr_ctrl/
25	tb.sv is renamed as tb_top	dinesha	5315d 04h	/sdr_ctrl/
24	Clean Up	dinesha	5315d 04h	/sdr_ctrl/
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	5316d 10h	/sdr_ctrl/
22	Pad sdram clock added	dinesha	5316d 10h	/sdr_ctrl/
21	Clean up	dinesha	5316d 10h	/sdr_ctrl/
20	8 Bit SDARM support is added	dinesha	5318d 04h	/sdr_ctrl/
19	8 Bit SDRAM Support added	dinesha	5318d 04h	/sdr_ctrl/
18	8 Bit SDRAM Support is added	dinesha	5318d 05h	/sdr_ctrl/
17	micron 8 bit memory models are added into svn	dinesha	5318d 05h	/sdr_ctrl/
16	8 Bit SDRAM Support is added	dinesha	5318d 05h	/sdr_ctrl/
15	Port cleanup	dinesha	5321d 05h	/sdr_ctrl/
14	Unnecessary device config are removed	dinesha	5321d 05h	/sdr_ctrl/
13	column bit are made progrmmable	dinesha	5321d 06h	/sdr_ctrl/
12	Column Bits are made programmable	dinesha	5321d 06h	/sdr_ctrl/
11	SDRAM Specification document added into SVN	dinesha	5324d 07h	/sdr_ctrl/
10	Waveform files are added into SVN	dinesha	5324d 07h	/sdr_ctrl/
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	5325d 06h	/sdr_ctrl/