URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 30

Rev	Log message	Author	Age	Path
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4465d 10h	/sdr_ctrl/
29	SDRAM top and core related run file list are added into svn	dinesha	4465d 11h	/sdr_ctrl/
28	SDRAM top and SDRAM Core Golden files are added into SVN	dinesha	4465d 11h	/sdr_ctrl/
27	Golden log file corresponds the SDRAM core level test case are added into svn	dinesha	4466d 09h	/sdr_ctrl/
26	invalid log files are removed	dinesha	4466d 09h	/sdr_ctrl/
25	tb.sv is renamed as tb_top	dinesha	4466d 09h	/sdr_ctrl/
24	Clean Up	dinesha	4466d 09h	/sdr_ctrl/
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	4467d 14h	/sdr_ctrl/
22	Pad sdram clock added	dinesha	4467d 14h	/sdr_ctrl/
21	Clean up	dinesha	4467d 14h	/sdr_ctrl/
20	8 Bit SDARM support is added	dinesha	4469d 09h	/sdr_ctrl/
19	8 Bit SDRAM Support added	dinesha	4469d 09h	/sdr_ctrl/
18	8 Bit SDRAM Support is added	dinesha	4469d 09h	/sdr_ctrl/
17	micron 8 bit memory models are added into svn	dinesha	4469d 09h	/sdr_ctrl/
16	8 Bit SDRAM Support is added	dinesha	4469d 09h	/sdr_ctrl/
15	Port cleanup	dinesha	4472d 10h	/sdr_ctrl/
14	Unnecessary device config are removed	dinesha	4472d 10h	/sdr_ctrl/
13	column bit are made progrmmable	dinesha	4472d 10h	/sdr_ctrl/
12	Column Bits are made programmable	dinesha	4472d 10h	/sdr_ctrl/
11	SDRAM Specification document added into SVN	dinesha	4475d 11h	/sdr_ctrl/