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[/] [sdr_ctrl/] - Rev 30

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Rev Log message Author Age Path
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4495d 02h /sdr_ctrl
29 SDRAM top and core related run file list are added into svn dinesha 4495d 02h /sdr_ctrl
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4495d 02h /sdr_ctrl
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4496d 00h /sdr_ctrl
26 invalid log files are removed dinesha 4496d 00h /sdr_ctrl
25 tb.sv is renamed as tb_top dinesha 4496d 01h /sdr_ctrl
24 Clean Up dinesha 4496d 01h /sdr_ctrl
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4497d 06h /sdr_ctrl
22 Pad sdram clock added dinesha 4497d 06h /sdr_ctrl
21 Clean up dinesha 4497d 06h /sdr_ctrl
20 8 Bit SDARM support is added dinesha 4499d 01h /sdr_ctrl
19 8 Bit SDRAM Support added dinesha 4499d 01h /sdr_ctrl
18 8 Bit SDRAM Support is added dinesha 4499d 01h /sdr_ctrl
17 micron 8 bit memory models are added into svn dinesha 4499d 01h /sdr_ctrl
16 8 Bit SDRAM Support is added dinesha 4499d 01h /sdr_ctrl
15 Port cleanup dinesha 4502d 02h /sdr_ctrl
14 Unnecessary device config are removed dinesha 4502d 02h /sdr_ctrl
13 column bit are made progrmmable dinesha 4502d 02h /sdr_ctrl
12 Column Bits are made programmable dinesha 4502d 02h /sdr_ctrl
11 SDRAM Specification document added into SVN dinesha 4505d 03h /sdr_ctrl
10 Waveform files are added into SVN dinesha 4505d 03h /sdr_ctrl
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4506d 03h /sdr_ctrl
8 test bench files are added into SVN dinesha 4506d 03h /sdr_ctrl
7 SDRAM Memory Models are added into SVN dinesha 4506d 03h /sdr_ctrl
6 Golden Log files are added into SVN dinesha 4506d 03h /sdr_ctrl
5 Run files are updated into SVN dinesha 4506d 03h /sdr_ctrl
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4507d 00h /sdr_ctrl
3 SDRAM controller core files are checked in dinesha 4513d 10h /sdr_ctrl
2 dinesha 4516d 02h /sdr_ctrl
1 The project and the structure was created root 4520d 02h /sdr_ctrl

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