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[/] [sdr_ctrl/] - Rev 36


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Rev Log message Author Age Path
36 Clean up dinesha 4321d 15h /sdr_ctrl
35 Updated the New Documents - ver 0.1 dinesha 4321d 17h /sdr_ctrl
34 Removed the older version dinesha 4321d 17h /sdr_ctrl
33 clean up dinesha 4321d 17h /sdr_ctrl
32 Debug is enable through +define dinesha 4323d 16h /sdr_ctrl
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4323d 16h /sdr_ctrl
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4323d 16h /sdr_ctrl
29 SDRAM top and core related run file list are added into svn dinesha 4323d 16h /sdr_ctrl
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4323d 16h /sdr_ctrl
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4324d 14h /sdr_ctrl
26 invalid log files are removed dinesha 4324d 15h /sdr_ctrl
25 is renamed as tb_top dinesha 4324d 15h /sdr_ctrl
24 Clean Up dinesha 4324d 15h /sdr_ctrl
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4325d 20h /sdr_ctrl
22 Pad sdram clock added dinesha 4325d 20h /sdr_ctrl
21 Clean up dinesha 4325d 20h /sdr_ctrl
20 8 Bit SDARM support is added dinesha 4327d 15h /sdr_ctrl
19 8 Bit SDRAM Support added dinesha 4327d 15h /sdr_ctrl
18 8 Bit SDRAM Support is added dinesha 4327d 15h /sdr_ctrl
17 micron 8 bit memory models are added into svn dinesha 4327d 15h /sdr_ctrl

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