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[/] [sdr_ctrl/] - Rev 40

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Rev Log message Author Age Path
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4527d 11h /sdr_ctrl/
39 Test Bench upgradation with bigger data burst size dinesha 4527d 11h /sdr_ctrl/
38 Port Name clean up dinesha 4528d 16h /sdr_ctrl/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4528d 18h /sdr_ctrl/
36 Clean up dinesha 4529d 09h /sdr_ctrl/
35 Updated the New Documents - ver 0.1 dinesha 4529d 10h /sdr_ctrl/
34 Removed the older version dinesha 4529d 10h /sdr_ctrl/
33 clean up dinesha 4529d 11h /sdr_ctrl/
32 Debug is enable through +define dinesha 4531d 10h /sdr_ctrl/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4531d 10h /sdr_ctrl/
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4531d 10h /sdr_ctrl/
29 SDRAM top and core related run file list are added into svn dinesha 4531d 10h /sdr_ctrl/
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4531d 10h /sdr_ctrl/
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4532d 08h /sdr_ctrl/
26 invalid log files are removed dinesha 4532d 08h /sdr_ctrl/
25 tb.sv is renamed as tb_top dinesha 4532d 09h /sdr_ctrl/
24 Clean Up dinesha 4532d 09h /sdr_ctrl/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4533d 14h /sdr_ctrl/
22 Pad sdram clock added dinesha 4533d 14h /sdr_ctrl/
21 Clean up dinesha 4533d 14h /sdr_ctrl/

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