Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 40


Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4319d 16h /sdr_ctrl
39 Test Bench upgradation with bigger data burst size dinesha 4319d 16h /sdr_ctrl
38 Port Name clean up dinesha 4320d 21h /sdr_ctrl
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4320d 23h /sdr_ctrl
36 Clean up dinesha 4321d 14h /sdr_ctrl
35 Updated the New Documents - ver 0.1 dinesha 4321d 15h /sdr_ctrl
34 Removed the older version dinesha 4321d 15h /sdr_ctrl
33 clean up dinesha 4321d 16h /sdr_ctrl
32 Debug is enable through +define dinesha 4323d 15h /sdr_ctrl
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4323d 15h /sdr_ctrl
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4323d 15h /sdr_ctrl
29 SDRAM top and core related run file list are added into svn dinesha 4323d 15h /sdr_ctrl
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4323d 15h /sdr_ctrl
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4324d 13h /sdr_ctrl
26 invalid log files are removed dinesha 4324d 13h /sdr_ctrl
25 is renamed as tb_top dinesha 4324d 14h /sdr_ctrl
24 Clean Up dinesha 4324d 14h /sdr_ctrl
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4325d 19h /sdr_ctrl
22 Pad sdram clock added dinesha 4325d 19h /sdr_ctrl
21 Clean up dinesha 4325d 19h /sdr_ctrl

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2023, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.