URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 45

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Rev	Log message	Author	Age	Path
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4471d 06h	/sdr_ctrl/
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4473d 04h	/sdr_ctrl/
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4473d 06h	/sdr_ctrl/
42	Bug fix in read access is fixed	dinesha	4473d 06h	/sdr_ctrl/
41	Updated Spec ver 0.1 is added back to svn	dinesha	4473d 08h	/sdr_ctrl/
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	4474d 01h	/sdr_ctrl/
39	Test Bench upgradation with bigger data burst size	dinesha	4474d 01h	/sdr_ctrl/
38	Port Name clean up	dinesha	4475d 06h	/sdr_ctrl/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4475d 08h	/sdr_ctrl/
36	Clean up	dinesha	4475d 22h	/sdr_ctrl/
35	Updated the New Documents - ver 0.1	dinesha	4476d 00h	/sdr_ctrl/
34	Removed the older version	dinesha	4476d 00h	/sdr_ctrl/
33	clean up	dinesha	4476d 01h	/sdr_ctrl/
32	Debug is enable through +define	dinesha	4478d 00h	/sdr_ctrl/
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4478d 00h	/sdr_ctrl/
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4478d 00h	/sdr_ctrl/
29	SDRAM top and core related run file list are added into svn	dinesha	4478d 00h	/sdr_ctrl/
28	SDRAM top and SDRAM Core Golden files are added into SVN	dinesha	4478d 00h	/sdr_ctrl/
27	Golden log file corresponds the SDRAM core level test case are added into svn	dinesha	4478d 22h	/sdr_ctrl/
26	invalid log files are removed	dinesha	4478d 22h	/sdr_ctrl/

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Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 45

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