OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 52

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
52 Documentation update for request control and transfer control block dinesha 4476d 04h /sdr_ctrl/
51 FPGA relating timing optimisation done dinesha 4476d 04h /sdr_ctrl/
50 Bug fix the request length is fixe dinesha 4478d 08h /sdr_ctrl/
49 clean up dinesha 4479d 07h /sdr_ctrl/
48 top-level cleanup dinesha 4479d 07h /sdr_ctrl/
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4479d 07h /sdr_ctrl/
46 test bench upgrade + rtl cleanup dinesha 4481d 08h /sdr_ctrl/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4481d 12h /sdr_ctrl/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4483d 10h /sdr_ctrl/
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4483d 12h /sdr_ctrl/
42 Bug fix in read access is fixed dinesha 4483d 12h /sdr_ctrl/
41 Updated Spec ver 0.1 is added back to svn dinesha 4483d 14h /sdr_ctrl/
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4484d 06h /sdr_ctrl/
39 Test Bench upgradation with bigger data burst size dinesha 4484d 07h /sdr_ctrl/
38 Port Name clean up dinesha 4485d 12h /sdr_ctrl/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4485d 13h /sdr_ctrl/
36 Clean up dinesha 4486d 04h /sdr_ctrl/
35 Updated the New Documents - ver 0.1 dinesha 4486d 06h /sdr_ctrl/
34 Removed the older version dinesha 4486d 06h /sdr_ctrl/
33 clean up dinesha 4486d 06h /sdr_ctrl/
32 Debug is enable through +define dinesha 4488d 05h /sdr_ctrl/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4488d 05h /sdr_ctrl/
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4488d 05h /sdr_ctrl/
29 SDRAM top and core related run file list are added into svn dinesha 4488d 06h /sdr_ctrl/
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4488d 06h /sdr_ctrl/
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4489d 04h /sdr_ctrl/
26 invalid log files are removed dinesha 4489d 04h /sdr_ctrl/
25 tb.sv is renamed as tb_top dinesha 4489d 04h /sdr_ctrl/
24 Clean Up dinesha 4489d 04h /sdr_ctrl/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4490d 09h /sdr_ctrl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.