URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 52

Rev	Log message	Author	Age	Path
32	Debug is enable through +define	dinesha	4489d 03h	/sdr_ctrl/
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4489d 03h	/sdr_ctrl/
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4489d 04h	/sdr_ctrl/
29	SDRAM top and core related run file list are added into svn	dinesha	4489d 04h	/sdr_ctrl/
28	SDRAM top and SDRAM Core Golden files are added into SVN	dinesha	4489d 04h	/sdr_ctrl/
27	Golden log file corresponds the SDRAM core level test case are added into svn	dinesha	4490d 02h	/sdr_ctrl/
26	invalid log files are removed	dinesha	4490d 02h	/sdr_ctrl/
25	tb.sv is renamed as tb_top	dinesha	4490d 02h	/sdr_ctrl/
24	Clean Up	dinesha	4490d 02h	/sdr_ctrl/
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	4491d 07h	/sdr_ctrl/