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[/] [sdr_ctrl/] - Rev 53

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Rev Log message Author Age Path
53 Test bench upgradation dinesha 4544d 19h /sdr_ctrl/
52 Documentation update for request control and transfer control block dinesha 4544d 19h /sdr_ctrl/
51 FPGA relating timing optimisation done dinesha 4544d 19h /sdr_ctrl/
50 Bug fix the request length is fixe dinesha 4546d 23h /sdr_ctrl/
49 clean up dinesha 4547d 22h /sdr_ctrl/
48 top-level cleanup dinesha 4547d 22h /sdr_ctrl/
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4547d 22h /sdr_ctrl/
46 test bench upgrade + rtl cleanup dinesha 4549d 23h /sdr_ctrl/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4550d 03h /sdr_ctrl/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4552d 01h /sdr_ctrl/
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4552d 03h /sdr_ctrl/
42 Bug fix in read access is fixed dinesha 4552d 03h /sdr_ctrl/
41 Updated Spec ver 0.1 is added back to svn dinesha 4552d 05h /sdr_ctrl/
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4552d 22h /sdr_ctrl/
39 Test Bench upgradation with bigger data burst size dinesha 4552d 22h /sdr_ctrl/
38 Port Name clean up dinesha 4554d 03h /sdr_ctrl/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4554d 04h /sdr_ctrl/
36 Clean up dinesha 4554d 19h /sdr_ctrl/
35 Updated the New Documents - ver 0.1 dinesha 4554d 21h /sdr_ctrl/
34 Removed the older version dinesha 4554d 21h /sdr_ctrl/

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