URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 58

Rev	Log message	Author	Age	Path
38	Port Name clean up	dinesha	4494d 03h	/sdr_ctrl/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4494d 04h	/sdr_ctrl/
36	Clean up	dinesha	4494d 19h	/sdr_ctrl/
35	Updated the New Documents - ver 0.1	dinesha	4494d 21h	/sdr_ctrl/
34	Removed the older version	dinesha	4494d 21h	/sdr_ctrl/
33	clean up	dinesha	4494d 21h	/sdr_ctrl/
32	Debug is enable through +define	dinesha	4496d 20h	/sdr_ctrl/
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4496d 20h	/sdr_ctrl/
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4496d 20h	/sdr_ctrl/
29	SDRAM top and core related run file list are added into svn	dinesha	4496d 20h	/sdr_ctrl/