URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 59

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
59	Control path request and data are register now for better FPGA timing	dinesha	4472d 13h	/sdr_ctrl/
58	Read Data is register on RD_FAST=0 case	dinesha	4472d 13h	/sdr_ctrl/
57	Synthesis constraints are added	dinesha	4473d 04h	/sdr_ctrl/
56	FPGA Synth optimisation	dinesha	4473d 05h	/sdr_ctrl/
55	FPGA Synthesis timing optimisation	dinesha	4473d 05h	/sdr_ctrl/
54	FPGA Timing Optimisation	dinesha	4476d 03h	/sdr_ctrl/
53	Test bench upgradation	dinesha	4477d 03h	/sdr_ctrl/
52	Documentation update for request control and transfer control block	dinesha	4477d 03h	/sdr_ctrl/
51	FPGA relating timing optimisation done	dinesha	4477d 03h	/sdr_ctrl/
50	Bug fix the request length is fixe	dinesha	4479d 07h	/sdr_ctrl/
49	clean up	dinesha	4480d 06h	/sdr_ctrl/
48	top-level cleanup	dinesha	4480d 06h	/sdr_ctrl/
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4480d 06h	/sdr_ctrl/
46	test bench upgrade + rtl cleanup	dinesha	4482d 07h	/sdr_ctrl/
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4482d 11h	/sdr_ctrl/
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4484d 09h	/sdr_ctrl/
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4484d 11h	/sdr_ctrl/
42	Bug fix in read access is fixed	dinesha	4484d 11h	/sdr_ctrl/
41	Updated Spec ver 0.1 is added back to svn	dinesha	4484d 13h	/sdr_ctrl/
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	4485d 06h	/sdr_ctrl/
39	Test Bench upgradation with bigger data burst size	dinesha	4485d 06h	/sdr_ctrl/
38	Port Name clean up	dinesha	4486d 11h	/sdr_ctrl/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4486d 13h	/sdr_ctrl/
36	Clean up	dinesha	4487d 04h	/sdr_ctrl/
35	Updated the New Documents - ver 0.1	dinesha	4487d 05h	/sdr_ctrl/
34	Removed the older version	dinesha	4487d 05h	/sdr_ctrl/
33	clean up	dinesha	4487d 06h	/sdr_ctrl/
32	Debug is enable through +define	dinesha	4489d 05h	/sdr_ctrl/
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4489d 05h	/sdr_ctrl/
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4489d 05h	/sdr_ctrl/

Browse

Tools

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 59

Filtering Options