URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 60

Rev	Log message	Author	Age	Path
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	4482d 04h	/sdr_ctrl/
39	Test Bench upgradation with bigger data burst size	dinesha	4482d 05h	/sdr_ctrl/
38	Port Name clean up	dinesha	4483d 10h	/sdr_ctrl/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4483d 11h	/sdr_ctrl/
36	Clean up	dinesha	4484d 02h	/sdr_ctrl/
35	Updated the New Documents - ver 0.1	dinesha	4484d 04h	/sdr_ctrl/
34	Removed the older version	dinesha	4484d 04h	/sdr_ctrl/
33	clean up	dinesha	4484d 04h	/sdr_ctrl/
32	Debug is enable through +define	dinesha	4486d 03h	/sdr_ctrl/
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4486d 03h	/sdr_ctrl/