URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 63

Rev	Log message	Author	Age	Path
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4492d 22h	/sdr_ctrl/
42	Bug fix in read access is fixed	dinesha	4492d 22h	/sdr_ctrl/
41	Updated Spec ver 0.1 is added back to svn	dinesha	4493d 00h	/sdr_ctrl/
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	4493d 17h	/sdr_ctrl/
39	Test Bench upgradation with bigger data burst size	dinesha	4493d 17h	/sdr_ctrl/
38	Port Name clean up	dinesha	4494d 22h	/sdr_ctrl/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4495d 00h	/sdr_ctrl/
36	Clean up	dinesha	4495d 14h	/sdr_ctrl/
35	Updated the New Documents - ver 0.1	dinesha	4495d 16h	/sdr_ctrl/
34	Removed the older version	dinesha	4495d 16h	/sdr_ctrl/