URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 70

Rev	Log message	Author	Age	Path
70	Warning Cleanup	dinesha	4017d 21h	/sdr_ctrl/
69	SDRAM address bit increased from 12 bit to 13 bit	dinesha	4017d 22h	/sdr_ctrl/
68	SDRAM Address bit increased from 12 bit to 13 bit	dinesha	4017d 22h	/sdr_ctrl/
67	time scale removed	dinesha	4087d 20h	/sdr_ctrl/
66	dwm tw, bl paramter are passed on the wb2sdrc module	dinesha	4335d 21h	/sdr_ctrl/
65	Updated Log file with CAS latency support 4,5	dinesha	4336d 05h	/sdr_ctrl/
64	CAS Latency support added for 4,5	dinesha	4336d 05h	/sdr_ctrl/
63	FPGA Bench mark results are added	dinesha	4455d 04h	/sdr_ctrl/
62	Synthesis constraint for simplify	dinesha	4455d 04h	/sdr_ctrl/
61	RTL file list are added into SVN	dinesha	4455d 05h	/sdr_ctrl/
60	warning cleanup	dinesha	4455d 05h	/sdr_ctrl/
59	Control path request and data are register now for better FPGA timing	dinesha	4455d 05h	/sdr_ctrl/
58	Read Data is register on RD_FAST=0 case	dinesha	4455d 05h	/sdr_ctrl/
57	Synthesis constraints are added	dinesha	4455d 19h	/sdr_ctrl/
56	FPGA Synth optimisation	dinesha	4455d 20h	/sdr_ctrl/
55	FPGA Synthesis timing optimisation	dinesha	4455d 21h	/sdr_ctrl/
54	FPGA Timing Optimisation	dinesha	4458d 18h	/sdr_ctrl/
53	Test bench upgradation	dinesha	4459d 19h	/sdr_ctrl/
52	Documentation update for request control and transfer control block	dinesha	4459d 19h	/sdr_ctrl/
51	FPGA relating timing optimisation done	dinesha	4459d 19h	/sdr_ctrl/