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[/] [sdr_ctrl/] - Rev 70

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Rev Log message Author Age Path
70 Warning Cleanup dinesha 4028d 07h /sdr_ctrl/
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4028d 08h /sdr_ctrl/
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 4028d 08h /sdr_ctrl/
67 time scale removed dinesha 4098d 06h /sdr_ctrl/
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4346d 07h /sdr_ctrl/
65 Updated Log file with CAS latency support 4,5 dinesha 4346d 15h /sdr_ctrl/
64 CAS Latency support added for 4,5 dinesha 4346d 15h /sdr_ctrl/
63 FPGA Bench mark results are added dinesha 4465d 14h /sdr_ctrl/
62 Synthesis constraint for simplify dinesha 4465d 14h /sdr_ctrl/
61 RTL file list are added into SVN dinesha 4465d 15h /sdr_ctrl/
60 warning cleanup dinesha 4465d 15h /sdr_ctrl/
59 Control path request and data are register now for better FPGA timing dinesha 4465d 15h /sdr_ctrl/
58 Read Data is register on RD_FAST=0 case dinesha 4465d 15h /sdr_ctrl/
57 Synthesis constraints are added dinesha 4466d 05h /sdr_ctrl/
56 FPGA Synth optimisation dinesha 4466d 06h /sdr_ctrl/
55 FPGA Synthesis timing optimisation dinesha 4466d 07h /sdr_ctrl/
54 FPGA Timing Optimisation dinesha 4469d 04h /sdr_ctrl/
53 Test bench upgradation dinesha 4470d 05h /sdr_ctrl/
52 Documentation update for request control and transfer control block dinesha 4470d 05h /sdr_ctrl/
51 FPGA relating timing optimisation done dinesha 4470d 05h /sdr_ctrl/
50 Bug fix the request length is fixe dinesha 4472d 09h /sdr_ctrl/
49 clean up dinesha 4473d 08h /sdr_ctrl/
48 top-level cleanup dinesha 4473d 08h /sdr_ctrl/
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4473d 08h /sdr_ctrl/
46 test bench upgrade + rtl cleanup dinesha 4475d 09h /sdr_ctrl/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4475d 13h /sdr_ctrl/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4477d 11h /sdr_ctrl/
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4477d 13h /sdr_ctrl/
42 Bug fix in read access is fixed dinesha 4477d 13h /sdr_ctrl/
41 Updated Spec ver 0.1 is added back to svn dinesha 4477d 15h /sdr_ctrl/

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