URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 71

Rev	Log message	Author	Age	Path
51	FPGA relating timing optimisation done	dinesha	4475d 06h	/sdr_ctrl/
50	Bug fix the request length is fixe	dinesha	4477d 10h	/sdr_ctrl/
49	clean up	dinesha	4478d 09h	/sdr_ctrl/
48	top-level cleanup	dinesha	4478d 09h	/sdr_ctrl/
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4478d 09h	/sdr_ctrl/
46	test bench upgrade + rtl cleanup	dinesha	4480d 10h	/sdr_ctrl/
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4480d 14h	/sdr_ctrl/
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4482d 12h	/sdr_ctrl/
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4482d 14h	/sdr_ctrl/
42	Bug fix in read access is fixed	dinesha	4482d 14h	/sdr_ctrl/