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[/] [sdr_ctrl/] - Rev 73


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Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 969d 06h /sdr_ctrl/
72 Command Clean up for model-sim mode dinesha 3962d 15h /sdr_ctrl/
71 Warning cleanup dinesha 4014d 07h /sdr_ctrl/
70 Warning Cleanup dinesha 4014d 07h /sdr_ctrl/
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4014d 08h /sdr_ctrl/
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 4014d 08h /sdr_ctrl/
67 time scale removed dinesha 4084d 07h /sdr_ctrl/
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4332d 07h /sdr_ctrl/
65 Updated Log file with CAS latency support 4,5 dinesha 4332d 15h /sdr_ctrl/
64 CAS Latency support added for 4,5 dinesha 4332d 15h /sdr_ctrl/
63 FPGA Bench mark results are added dinesha 4451d 14h /sdr_ctrl/
62 Synthesis constraint for simplify dinesha 4451d 14h /sdr_ctrl/
61 RTL file list are added into SVN dinesha 4451d 15h /sdr_ctrl/
60 warning cleanup dinesha 4451d 15h /sdr_ctrl/
59 Control path request and data are register now for better FPGA timing dinesha 4451d 15h /sdr_ctrl/
58 Read Data is register on RD_FAST=0 case dinesha 4451d 15h /sdr_ctrl/
57 Synthesis constraints are added dinesha 4452d 06h /sdr_ctrl/
56 FPGA Synth optimisation dinesha 4452d 07h /sdr_ctrl/
55 FPGA Synthesis timing optimisation dinesha 4452d 07h /sdr_ctrl/
54 FPGA Timing Optimisation dinesha 4455d 05h /sdr_ctrl/

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