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[/] [sdr_ctrl/] [trunk/] - Rev 73

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Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 1195d 04h /sdr_ctrl/trunk/
72 Command Clean up for model-sim mode dinesha 4188d 13h /sdr_ctrl/trunk/
71 Warning cleanup dinesha 4240d 05h /sdr_ctrl/trunk/
70 Warning Cleanup dinesha 4240d 05h /sdr_ctrl/trunk/
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4240d 06h /sdr_ctrl/trunk/
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 4240d 06h /sdr_ctrl/trunk/
67 time scale removed dinesha 4310d 04h /sdr_ctrl/trunk/
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4558d 05h /sdr_ctrl/trunk/
65 Updated Log file with CAS latency support 4,5 dinesha 4558d 13h /sdr_ctrl/trunk/
64 CAS Latency support added for 4,5 dinesha 4558d 13h /sdr_ctrl/trunk/
63 FPGA Bench mark results are added dinesha 4677d 12h /sdr_ctrl/trunk/
62 Synthesis constraint for simplify dinesha 4677d 12h /sdr_ctrl/trunk/
61 RTL file list are added into SVN dinesha 4677d 13h /sdr_ctrl/trunk/
60 warning cleanup dinesha 4677d 13h /sdr_ctrl/trunk/
59 Control path request and data are register now for better FPGA timing dinesha 4677d 13h /sdr_ctrl/trunk/
58 Read Data is register on RD_FAST=0 case dinesha 4677d 13h /sdr_ctrl/trunk/
57 Synthesis constraints are added dinesha 4678d 03h /sdr_ctrl/trunk/
56 FPGA Synth optimisation dinesha 4678d 04h /sdr_ctrl/trunk/
55 FPGA Synthesis timing optimisation dinesha 4678d 05h /sdr_ctrl/trunk/
54 FPGA Timing Optimisation dinesha 4681d 02h /sdr_ctrl/trunk/

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