Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] - Rev 73


Filtering Options

Clear current filter

Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 907d 21h /sdr_ctrl/trunk/
72 Command Clean up for model-sim mode dinesha 3901d 06h /sdr_ctrl/trunk/
71 Warning cleanup dinesha 3952d 22h /sdr_ctrl/trunk/
70 Warning Cleanup dinesha 3952d 22h /sdr_ctrl/trunk/
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 3952d 23h /sdr_ctrl/trunk/
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 3952d 23h /sdr_ctrl/trunk/
67 time scale removed dinesha 4022d 21h /sdr_ctrl/trunk/
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4270d 22h /sdr_ctrl/trunk/
65 Updated Log file with CAS latency support 4,5 dinesha 4271d 06h /sdr_ctrl/trunk/
64 CAS Latency support added for 4,5 dinesha 4271d 06h /sdr_ctrl/trunk/
63 FPGA Bench mark results are added dinesha 4390d 05h /sdr_ctrl/trunk/
62 Synthesis constraint for simplify dinesha 4390d 05h /sdr_ctrl/trunk/
61 RTL file list are added into SVN dinesha 4390d 06h /sdr_ctrl/trunk/
60 warning cleanup dinesha 4390d 06h /sdr_ctrl/trunk/
59 Control path request and data are register now for better FPGA timing dinesha 4390d 06h /sdr_ctrl/trunk/
58 Read Data is register on RD_FAST=0 case dinesha 4390d 06h /sdr_ctrl/trunk/
57 Synthesis constraints are added dinesha 4390d 20h /sdr_ctrl/trunk/
56 FPGA Synth optimisation dinesha 4390d 21h /sdr_ctrl/trunk/
55 FPGA Synthesis timing optimisation dinesha 4390d 22h /sdr_ctrl/trunk/
54 FPGA Timing Optimisation dinesha 4393d 19h /sdr_ctrl/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.