OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] - Rev 27

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4525d 21h /sdr_ctrl/trunk/
26 invalid log files are removed dinesha 4525d 21h /sdr_ctrl/trunk/
25 tb.sv is renamed as tb_top dinesha 4525d 21h /sdr_ctrl/trunk/
24 Clean Up dinesha 4525d 21h /sdr_ctrl/trunk/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4527d 02h /sdr_ctrl/trunk/
22 Pad sdram clock added dinesha 4527d 02h /sdr_ctrl/trunk/
21 Clean up dinesha 4527d 02h /sdr_ctrl/trunk/
20 8 Bit SDARM support is added dinesha 4528d 21h /sdr_ctrl/trunk/
19 8 Bit SDRAM Support added dinesha 4528d 21h /sdr_ctrl/trunk/
18 8 Bit SDRAM Support is added dinesha 4528d 21h /sdr_ctrl/trunk/
17 micron 8 bit memory models are added into svn dinesha 4528d 21h /sdr_ctrl/trunk/
16 8 Bit SDRAM Support is added dinesha 4528d 21h /sdr_ctrl/trunk/
15 Port cleanup dinesha 4531d 22h /sdr_ctrl/trunk/
14 Unnecessary device config are removed dinesha 4531d 22h /sdr_ctrl/trunk/
13 column bit are made progrmmable dinesha 4531d 22h /sdr_ctrl/trunk/
12 Column Bits are made programmable dinesha 4531d 23h /sdr_ctrl/trunk/
11 SDRAM Specification document added into SVN dinesha 4534d 23h /sdr_ctrl/trunk/
10 Waveform files are added into SVN dinesha 4534d 23h /sdr_ctrl/trunk/
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4535d 23h /sdr_ctrl/trunk/
8 test bench files are added into SVN dinesha 4535d 23h /sdr_ctrl/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.